1. Field of the Invention
This invention relates to DDR3 chip packages, and more particularly, to DDR3 chips wherein bank addresses can be logically reassigned.
2. Description of the Prior Art
Double Data Rate (DDR) Technology allows data transfer to occur on both a rising and a falling edge of a clock. This means that the frequency of data transfer relative to a memory bus clock rate is doubled. DDR3 technology looks set to replace DDR2 chips, by offering reduced power consumption and increased internal data bus widths. Whereas DDR2 chips can only prefetch 4 bits per clock, DDR3 chips can prefetch 8 bits per clock. The number of logical banks in a DDR3 chip is also 8, compared to DDR2's 4.
The DDR3 chip can operate in X4, X8 or X16 modes. In order to minimize test costs, DDR3 chips have an X16 wide datapath, although the maximum required width for operation is X8. For an X16 wide datapath, bank addresses are assigned according to a half banking scheme, wherein each bank consists of two half banks physically located on different halves of the chip. In X4 and X8 modes, only one half of the banks will have datalines driven to a data block located at the centre of the chip, resulting in 64 bits arriving at the central data block—in other words, only one half of the chip will be used. In X16 mode, datalines are driven from both halves of the chip, resulting in 128 bits arriving at the central data block.
Please refer to FIG. 1, which is an illustration of a prior art DDR3 chip 100, showing the bank addresses. A typical DDR3 chip also comprises a clock and a memory controller, but these elements are omitted for simplicity. The DDR3 chip 100 comprises eight banks, which are each divided into half-banks and arranged in different parts of the chip, such that there are eight ‘upper’ half banks 0U, 1U, 2U, 3U, 4U, 5U, 6U and 7U, and eight ‘downer’ half banks 0D, 1D, 2D, 3D, 4D, 5D, 6D and 7D. The RIB (not an acronym) refers to the global wordline circuitry which vertically separates the array banks. The DDR3 chip may have a column (COL) or single subarray access (SSA) architecture. The bank array surrounds the pads at the centre. The DDR3 chip 100 also comprises four spokes: Spoke UL (upper left), Spoke UR (upper right), Spoke DL (downer left) and Spoke DR (downer right). Each spoke is shared by four half-banks. As mentioned before, in X4 or X8 modes, data will only be driven from one half of the chip. For example, in X4 mode, the half-banks 4U, 5U, 6U and 7U will be opened and closed in a sequential fashion. As can be seen from the diagram, Spoke UR consists of these 4 half banks: 4U, 5U, 6U and 7U. In the X4 and X8 modes, as only half of the chip is in use, when there is constant toggling between these banks, there will be large voltage (IR, where Ohm's Law states that V=I*R, and IR represents the voltage drop as a current passes through a resistance) drops along the spoke region.